1. Field of Invention
The present invention relates to image sensors, and more particularly, to image sensors that allow varying degrees of resolution.
2. Description of the Prior Art
Conventional Charge Coupled Device (CCD) image sensors are comprised of an image sensing array and a transfer readout region. Typically these devices may have a shift register which comprises the readout region for each array of photodetectors. In the case of linear image sensors, there is typically one or two shift registers for a linear array of photodetectors, and typically one CCD "cell" for each photo detector. Each CCD cell may contain several electrodes to perform the shifting function.
CCD image sensors operate in the manner described below. Incident light photons penetrate into silicon based photodetectors resulting in the generation of electron-hole pairs. The electrons that are generated, at a rate proportional to the local light intensity, are collected either at the photo site or in an adjacent storage region. The electrons are then transferred through a transfer region into a CCD shift register in a parallel fashion (all charge packets are simultaneously transferred to their respective shift register "cell", thereby maintaining spatial integrity of the information). The individual charge packets are then shifted serially to an output device at one end of the shift register by means of shift register clock signals. It is therefore imperative that the shift register clocks contain enough cycles to completely read out all charge packets. If the clocks have an insufficient number of cycles to completely read out all the charge packets, then some packets of information will remain in the shift register at the last location to which they were shifted. This remaining charge will subsequently be added to the charge from the next line of image information, thereby corrupting the spatial information of the image.
In some applications high speed and lower resolution may be preferred to a higher resolution approach. It may then be desirable to use the same sensor in both higher and lower resolution applications by using only a portion of the image area for the lower resolution applications. However, as mentioned above, all the pixel information within CCD devices must be shifted out of the devices. Therefore, in lower resolution applications, once the required pixels are read out of the device, the rest of the charge packets must still be clocked out and discarded. This increases the time required to process the information from an image and presents a problem in systems that must operate at high speeds and can not afford the added time.
Solid state image sensors, particularly charge coupled device (CCD) imagers, disclosed by prior art are similar to the type illustrated in FIG. 1a and 1b. The imager is comprised of an array of photosites, a transfer region, one or more CCD shift registers, and an output amplifier. This type of imager operates by absorbing incident light photons and generating electrons at the photo site at a rate equivalent to the local light intensity. These electrons are then transferred through the transfer region into the shift register in a parallel manner. The shift register is then clocked to transport the individual charge packets, in a serial manner, to the output section. It is therefore evident for the single shift register case of FIG. 1a that the register must be clocked more than `m` times, or charge packets will be left behind in the register. Similarly, for the dual register case of FIG. 1b, M/2 cycles must be completed to read out all of the signal charge. This type of architecture therefore forces the user to allow enough time to completely read out the entire register.
FIG. 2 is an illustration of a prior art device having adjustable resolution features. In this architecture, the antiblooming features of the device are used to implement a variable resolution scheme. The antiblooming drain is located adjacent to the photodetectors and is used to drain charges from the CCD cells not used in creating an image. The charges from these unwanted cells are routed through to the antiblooming drain according to the selection features implemented by the user. The features of this prior art device are such that horizontal registers contain an isolation gate to achieve the variable levels of resolution. When the isolation gate is biased such that the channel potential is lower than the adjacent gate in the register, the charge packets to the right of the isolation gate will be read out via amplifiers, but the packets to the left of the isolation gate will be drained back through the antiblooming structure of the device, labeled Vsink. This architecture has the drawbacks that it is complex to build and requires many precise clock signals to control all the associated gates. The device of FIG. 2 requires a control signal that can be switched between a D.C. level, and the horizontal clock. The D.C. signal is required for the lower resolution mode and a horizontal clock signal is required for higher resolution mode. Furthermore, the device of FIG. 2 requires dual transfer electrodes, an antiblooming gate and a drain for each pixel. This increases the cell size, complexity and reduces the device yield.
It should be evident from the foregoing discussion that there remains a need within the prior art for variable resolution devices that do not leave extraneous charges within the device and that will provide higher speeds at lower resolution than is currently available with existing prior art devices. The present invention addresses the shortcomings of the prior art in providing such a device.